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Preliminary Technical Data
Table 34. ACCMODE Register (0x0F)
ADE7566/ADE7569
Bit No.
7 to 6
5
Mnemonic
Reserved
VARSIGN 1
Default
0
0
Description
Reserved.
Configuration bit to select event that triggers a reactive power sign interrupt. If set to 0, VARSIGN
interrupt occurs when reactive power changes from positive to negative. If set to 1, VARSIGN interrupt
occurs when reactive power changes from negative to positive.
4
APSIGN
0
Configuration bit to select event that triggers an active power sign interrupt. If set to 0, APSIGN interrupt
occurs when active power changes from positive to negative. If set to 1, APSIGN interrupt occurs when
active power changes from negative to positive.
3
2
ABSVARM 1
SAVARM 1
0
0
Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power
is positive, VAR is accumulated as it is. If active power is negative, the sign of the VAR is reversed for the
accumulation. This accumulation mode affects both the VAR registers (VARHR, RVARHR, LVARHR) and the
pulse output when connected to VAR. 1
1
0
POAM
ABSAM
0
0
Logic 1 enables positive only accumulation of active power in energy register and pulse output.
Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
1
This function is not available in the ADE7566 part.
Table 35. GAIN Register (0x1B)
Bit No.
7 to 5
Mnemonic
PGA2[2:0]
Default
000
Description
These bits define the voltage channel input gain.
PGA2[2:0] Result
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
4
3
Reserved
CFSIGN_OPT
0
0
Reserved.
This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is
implemented.
CFSIGN_OPT Result
0 Filtered power signal
1 On a per CF pulse basis
2 to 0
PGA1[2:0]
000
These bits define the current channel input gain.
PGA1[2:0] Result
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
Table 36. Interrupt Status Register 1 SFR (MIRQSTL, 0xDC)
Bit No.
7
6-5
4
3
2
1
0
Interrupt Flag
ADEIRQFLAG
Reserved
VARSIGN 1
APSIGN
VANOLOAD
RNOLOAD 1
APNOLOAD
Description
This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt are set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
Reserved.
Logic 1 indicates that the reactive power sign has changed according to the configuration of ACCMODE register.
Logic 1 indicates that the active power sign has changed according to the configuration of ACCMODE register.
Logic 1 indicates that an interrupt has been caused by apparent power no-load detected. This interrupt is also
used to reflect the part entering the I rms no load mode.
Logic 1 indicates that an interrupt has been caused by reactive power no-load detected.
Logic 1 indicates that an interrupt has been caused by active power no-load detected.
1
This function is not available in the ADE7566 part.
Rev. PrA | Page 39 of 136
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